This invention is in the field of semiconductor integrated circuits, and is more specifically directed to the construction of transistors in such circuits.
A continuing trend in the field of electronic devices and systems is the integration of system functions into fewer integrated circuits. Larger-scale integration provides improved device and system performance, because of such factors as the excellent matching among transistors within the same integrated circuit, the very short conduction path lengths among functions on the same integrated circuit, and the elimination of interface circuitry that is necessary for communication of signals between separate integrated circuits. These benefits are attained along with the significantly lower manufacturing cost with these fewer integrated circuits in the system. Ultimately, the goal continues to be the so-called “system on a chip”, in which all electronic functions of the end system are implemented within a single integrated circuit.
However, the integration of many system functions into fewer integrated circuits is difficult for certain types of electronic systems, especially those that must interface with relatively high voltages, such as communications systems. For example, modems (modulator/demodulators) must be compatible with relatively high voltages that are required by, or may be present on, telephone or cable lines. Wireless telephone handsets also require the generation of signals at relatively high output voltages, consistent with strong output signal power levels for good communications. Conversely, modern high-performance logic and memory circuits operate at decreasing power supply voltages, permitting high density integration of today's complex functionality by way of extremely small transistors, which have structures that cannot tolerate high voltages. For example, modern high-performance metal-oxide-semiconductor (MOS) transistors have extremely thin gate oxide layers, and also extremely shallow junctions, both of which can be easily damaged by overvoltage. These colliding trends cause a tradeoff between high-voltage robustness, on one hand, and device density and performance, on the other hand.
One transistor type that has been developed in recent years to address the problem of high voltages applied to small-geometry transistors is the drain-extended MOS (“DEMOS”) transistor. An example of a conventional drain-extended MOS transistor is shown in FIGS. 1a and 1b, and will now be described.
The transistor of FIGS. 1a and 1b is an n-channel DEMOS device, formed at a surface of lightly-doped substrate 2. This exemplary structure, as typical in the art for integrated circuits constructed according to complementary MOS (CMOS) technology, is formed according to a conventional twin-well process, in which p-type well region 4 and n-type well region 6 are formed at the surface of substrate 2. Both in the illustrated location and elsewhere in the integrated circuit, wells 4, 6, serve as the body region for n-channel MOS and p-channel MOS transistors, respectively, and as such are typically relatively lightly doped. Field oxide structures 9a, 9b are formed, by local oxidation of silicon (LOCOS) or by deposition and etching, at those locations of the surface of wells 4, 6 that are to isolate conductive regions from one another. The conductive regions of the surface of wells 4, 6 that are isolated by field oxide structures 9a, 9b are typically referred to as “moat” regions, and serve as the active regions (source, drain, and channel) of MOS devices, as known in the art. In this conventional example, doped regions 13 are disposed beneath field oxide structures 9, and are formed by the well-known “channel stop” ion implant to enhance the isolation provided by field oxide regions 9. Channel stop doped region 13p is a p-type region underlying field oxide structure 9a in p-well 4, and is more heavily doped than is p-well 4 to provide a higher p-type surface concentration in the isolation region underlying field oxide structure 9a; similarly, channel stop doped region 13n is a more heavily doped n-type region underlying field oxide structure 9b in n-well 6, to provide a higher n-type surface concentration in the isolation region underlying field oxide structure 9b. 
The active portions of this conventional DEMOS device are formed by self-aligned ion implantation at the surface of wells 4, 6. In this example, gate electrode 15 is a patterned layer of polysilicon, metal, silicide-clad polysilicon, or another known conductive material suitable for use as a transistor gate, and is disposed over gate oxide layer 11. Sidewall insulating filaments may be disposed along the edges of gate electrode 15, as used in the formation of graded junctions in the well-known manner. Source region 10 is a heavily-doped n-type region that is formed by ion implantation in a self-aligned manner relative to gate electrode 15 and field oxide structure 9a at the surface of p-well 4. Drain region 12 is a heavily doped n-type region formed by ion implantation into the surface of n-well 6, self-aligned relative to field oxide structure 9b, preferably using the same implant or implants as used to form source region 10. Similarly, backgate contact region 8 is a heavily-doped p-type region formed at a selected location of well 8, by way of ion implantation into a selected location of the surface of p-well 4, self-aligned relative to field oxide structure 9a. 
Overlying insulator layer 7 is disposed over all of the underlying structures, including gate electrode 15; field oxide structures 9; and source, drain, and backgate contact regions 10, 12, 8 respectively. Contact openings C are etched through insulator layer 7 at selected locations, and metal is then sputter deposited or evaporated overall, and etched in the conventional manner to form conductors BG, S, and D as shown in FIG. 1a. 
As mentioned above, the conventional transistor of FIGS. 1a and 1b is a drain-extended device. This drain extension is implemented by field oxide structure 9b that is disposed between drain region 12 and source region 10, on the drain end of the channel, and onto which gate electrode 15 overlaps. As shown in FIG. 1a, n-well 6 extends beyond field oxide structure 9b and has an edge underlying gate electrode 15. When transistor is turned on by the application of a positive voltage to gate electrode 15, electrons conduct from source region 10 toward the higher voltage at drain region 12 along the channel formed under gate oxide 11 by the voltage on gate electrode 15. Upon reaching n-well 6, the inversion channel is no longer present, but the electrons continue to drift toward drain region 12. As such, the portion of n-well 6 between drain region 12 and the channel region formed in p-well 4 is referred to as the “drift region” of the DEMOS device, and is shown in FIG. 1a as drift region DFT.
As known in the art, drain-extended MOS devices such as that shown in FIGS. 1a and 1b are capable of tolerating the application of higher drain-to-source voltages than are “regular” MOS devices that have similar geometries, gate oxide thicknesses, junction depths, but that are not drain-extended. This higher voltage can be tolerated because of the presence of drift region DFT, as shown in FIG. 1a, which effectively moves highly-doped drain region 12 from the body region of the device formed by p-well 4 in this example. Rather, the metallurgical drain-to-body junction of this DEMOS device is at the junction between p-well 4 and n-well 6, both of which are relatively lightly doped. The reverse breakdown voltage of the devices is thus much higher than for a conventional device in which the metallurgical junction would be between drain region 12 and p-well 4. In addition, the drain-side edge of gate electrode 15 is moved away from the conduction channel, protecting this edge and the underlying gate oxide 11 from the high electric fields that may be present at high drain voltages. In addition, as shown in FIG. 1b, the channel width of the conventional DEMOS device is quite large, even relative to the relatively long channel length between the source and the drift region, permitting this device to conduct a relatively large current when on.
Because of these effects, conventional DEMOS devices such as the n-channel transistor illustrated in FIGS. 1a and 1b have become popular in mixed-signal (i.e., analog and digital) integrated circuits, particularly those in which the digital transistors are required to have maximum performance but in which some transistors may be required to tolerate or source high voltages. An example of the application of a DEMOS transistor such as that shown in FIGS. 1a and 1b is for driving the gate of an output driver transistor, particularly where the gate voltage of the output device is to be driven to a voltage higher than its drain, such that the output voltage swing of the integrated circuit can be fully rail-to-rail.
It has been observed, however, that many conventional DEMOS devices are vulnerable to irreversible damage once they have enter a reverse breakdown condition. FIG. 2 qualitatively illustrates the current-voltage breakdown characteristics of a typical DEMOS device, constructed according to the conventional arrangement such as shown in FIGS. 1a and 1b. These characteristics are based on actual measurements of a conventional DEMOS n-channel device, with its gate and source at ground, and its drain voltage swept to positive levels relative to the gate and source. In this “off” condition for an enhancement mode DEMOS device, significant source-drain conduction does not begin until reverse breakdown.
Sweep SW1 illustrates a measured current-voltage characteristic for a first sweep of drain voltage relative to gate and source. By way of reference, the “knee” voltage at which significant source-drain current begins in sweep SW1 is at a drain voltage of about 50 volts, which is the reverse breakdown voltage observe for this sweep. Even with the source-drain current limited to about 1 μA, the next breakdown voltage sweep resulted in a characteristic as shown by sweep SW2, in which breakdown conduction begins virtually with any positive drain voltage, at relatively high current levels. The obvious conclusion from these two sweeps SW1 and SW2 is that the DEMOS device was damaged when entering reverse breakdown even a single time.
This breakdown damage has been observed by others in the art. Aur and Chatterjee, “Robustness of LDD nMOS Transistors Subjected to Measurement of Drain Breakdown Voltage”, Extended Abstracts of the 22nd Conference on Solid State Devices and Materials, Paper C-6-8 (1990), pp. 319-22, describes this phenomenon. While the cause of this breakdown damage is not exactly known, it is believed that this breakdown damage is due to the breakdown occurring in a highly localized manner within the device. Such a highly localized breakdown can trigger the conduction of the parasitic n-p-n bipolar transistor formed by drain 12 and n-well 6 as the collector, p-well 4 as the base, and source region 10 as the emitter. Conduction of this parasitic n-p-n transistor can cause further current crowding, which eventually leads to filamentation, and increase in current flow between drain and source. This theory remains consistent with current observations.
Various techniques for reducing the vulnerability of DEMOS devices to this breakdown damage by reducing the ability of the parasitic bipolar device to conduct, are known in the art. One such approach is to increase the doping concentration of the body region of the DEMOS device, thus increasing the doping concentration of the base of the parasitic bipolar device and inhibiting its conduction. However, the doping concentration of the wells in regular (i.e., non-drain-extended) MOS devices cannot be increased without adversely affecting the performance of those devices; accordingly, the formation of different well regions for the DEMOS and normal MOS devices requires additional mask and implant steps, and is thus quite costly. Another known approach is to apply a negative voltage bias to the body region of the DEMOS device, ensuring that the base-emitter junction of the parasitic bipolar device does not forward bias and thus preventing parasitic bipolar conduction. However, this negative backgate bias prevents the sharing of the well of the DEMOS device with normal MOS devices, and also will change the threshold voltage of the transistors which may, in turn, require adjustment of the gate oxide thickness. Another known approach is to increase the channel length of the DEMOS device, specifically by increasing the overlap region between the gate electrode and the active channel region to further inhibit bipolar conduction; however, this approach obviously increases the on-resistance of the DEMOS devices.
Another known technique for limiting breakdown damage in conventional DEMOS devices is to integrate the backgate contact region with the source region of the device, by alternating n+ and p+ regions adjacent to one another at the location of source region 10 in FIGS. 1a and 1b. The same overlying metal conductor contacts these alternating regions, thus making contact to the p+ region in the p-well to establish the backgate bias and to the n+ source region within the p-well. This arrangement ensures that the applied backgate bias relative to the source is exactly zero volts, which inhibits the parasitic bipolar conduction by preventing the base-emitter junction from becoming forward biased. However, this integrated source construction of course constrains the DEMOS devices to have a zero volt backgate bias, and prevents the fabrication of symmetric p-channel and n-channel DEMOS transistors in the same integrated circuit.